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dual, low noise, single-supply variable gain amplifier ad605 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 2 independent linear-in-db channels input noise at maximum gain: 1.8 nv/hz, 2.7 pa/hz bandwidth: 40 mhz (C3 db) differential input absolute gain range programmable C14 db to +34 db (fbk shorted to out) through 0 db to 48 db (fbk open) variable gain scaling: 20 db/v through 40 db/v stable gain with temperature and supply variations single-ended unipolar gain control output common mode independently set power shutdown at lower end of gain control single 5 v supply low power: 90 mw/channel drives adcs directly applications ultrasound and sonar time-gain controls high performance agc systems signal measurement functional block diagram precision passive input attenuator fixed gain amplifier +34.4db differential attenuator 0 to ?48.4db out vocm vgn vref +in ?in gain control and scaling fbk ad605 0 0541-001 figure 1. general description the ad605 is a low noise, accurate, dual channel, linear-in-db variable gain amplifier, optimized for any application requiring high performance, wide bandwidth variable gain control. operating from a single 5 v supply, the ad605 provides differential inputs and unipolar gain control for ease of use. added flexibility is achieved with a user-determined gain range and an external reference input that provides user-determined gain scaling (db/v). the high performance linear-in-db response of the ad605 is achieved with the differential input, single-supply, exponential amplifier (dsx-amp) architecture. each of the dsx-amps comprise a variable attenuator of 0 db to ?48.4 db followed by a high speed fixed gain amplifier. the attenuator is based on a 7-stage r-1.5r ladder network. the attenuation between tap points is 6.908 db, and 48.360 db for the entire ladder network. the dsx-amp architecture results in 1.8 nv/hz input noise spectral density and accepts a 2.0 v input signal when vocm is biased at vp/2. each independent channel of the ad605 provides a gain range of 48 db that can be optimized for the application. gain ranges between ?14 db to +34 db and 0 db to +48 db can be selected by a single resistor between pin fbk and pin out. the lower and upper gain ranges are determined by shorting pin fbk to pin out, or leaving pin fbk unconnected, respectively. the two channels of the ad605 can be cascaded to provide 96 db of very accurate gain range in a monolithic package. the gain control interface provides an input resistance of approximately 2 m and scale factors from 20 db/v to 30 db/v for a vref input voltage of 2.5 v to 1.67 v, respectively. note that scale factors up to 40 db/v are achievable with reduced accuracy for scales above 30 db/v. the gain scales linearly in db with control voltages (vgn) of 0.4 v to 2.4 v for the 20 db/v scale and 0.20 v to 1.20 v for the 40 db/v scale. when vgn is <50 mv, the amplifier is powered down to draw 1.9 ma. under normal operation, the quiescent supply current of each amplifier channel is only 18 ma. the ad605 is available in 16-lead pdip and 16-lead soic_n and is guaranteed for operation over the ?40c to +85c temperature range.
ad605 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics (per channel) ................... 7 theory of operation ...................................................................... 13 differential ladder (attenuator) .............................................. 14 ac coupling ............................................................................... 14 gain control interface ............................................................... 14 active feedback amplifier (fixed gain amp) ...................... 15 applications ..................................................................................... 16 connecting two amplifiers to double the gain range ....... 16 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 1/06rev. c to rev. d updated format..................................................................universal changes to table 2............................................................................ 5 changes to the differential ladder (attenuator) section......... 14 updated the outline dimensions ................................................ 18 changes to the ordering guide.................................................... 19 7/04rev. b to rev. c edits to general description........................................................... 1 edits to specifications ...................................................................... 2 edits to ordering guide .................................................................. 3 change to tpc 22............................................................................. 6 updated outline dimensions ....................................................... 12
ad605 rev. d | page 3 of 20 specifications each channel @ t a = 25c, v s = 5 v, r s = 50 , r l = 500 , c l = 5 pf, vref = 2.5 v (scaling = 20 db/v), ?14 db to +34 db gain range, unless otherwise noted. table 1. ad605a ad605b parameter conditions min typ max min typ max unit input characteristics input resistance 175 40 175 40 input capacitance 3.0 3.0 pf peak input voltage at minimum gain 2.5 2.5 2.5 2.5 v input voltage noise vgn = 2.9 v 1.8 1.8 nv/hz input current noise vgn = 2.9 v 2.7 2.7 pa/hz noise figure r s = 50 , f = 10 mhz, vgn = 2.9 v 8.4 8.4 db r s = 200 , f = 10 mhz, vgn = 2.9 v 12 12 db common-mode rejection ratio f = 1 mhz, vgn = 2.65 v ?20 ?20 db output characteristics ?3 db bandwidth constant with gain 40 40 mhz slew rate vgn = 1.5 v, output = 1 v step 170 170 v/s output signal range r l 500 2.5 1.5 2.5 1.5 v output impedance f = 10 mhz 2 2 output short-circuit current 40 40 ma harmonic distortion vgn = 1 v, v out = 1 v p-p hd2 f = 1 mhz ?64 ?64 dbc hd3 f = 1 mhz ?68 ?68 dbc hd2 f = 10 mhz ?51 ?51 dbc hd3 f = 10 mhz ?53 ?53 dbc two-tone intermodulation distortion (imd) r s = 0 , vgn = 2.9 v, v out = 1 v p-p f = 1 mhz ?72 ?72 dbc f = 10 mhz ?60 ?60 dbc 1 db compression point f = 10 mhz, vgn = 2.9 v, output referred +15 +15 dbm third-order intercept f = 10 mhz, vgn = 2.9 v, v out = 1 v p-p, input referred ?1 ?1 dbm channel-to-channel crosstalk ch1: vgn = 2.65 v, inputs shorted, ch2: vgn = 1.5 v (mid gain), f = 1 mhz, v out = 1 v p-p ?70 ?70 db group delay variation 1 mhz < f < 10 mhz, full gain range 2.0 2.0 ns vocm input resistance 45 45 k accuracy absolute gain error ?14 db to ?11 db 0.25 v < vgn < 0.40 v ?1.2 +1.0 +3.0 C1.2 +0.75 +3.0 db ?11 db to +29 db 0.40 v < vgn < 2.40 v ?1.0 0.3 +1.0 C1.0 0.2 +1.0 db +29 db to +34 db 2.40 v < vgn < 2.65 v ?3.5 ?1.25 +1.2 C3.5 ?1.25 +1.2 db gain scaling error 0.4 v < vgn < 2.4 v 0.25 0.25 db/v output offset voltage vref = 2.500 v, vocm = 2.500 v ?50 30 +50 C50 30 +50 mv output offset variation vref = 2.500 v, vocm = 2.500 v 30 95 30 50 mv
ad605 rev. d | page 4 of 20 ad605a ad605b parameter conditions min typ max min typ max unit gain control interface gain scaling factor vref = 2.5 v, 0.4 v < vgn < 2.4 v 19 20 21 19 20 21 db/v vref = 1.67 v 30 30 db/v gain range fbk short to out ?14 to +34 ?14 to +34 db fbk open 0 to 48 0 to 48 db input voltage (vgn) range 20 db/v, vref = 2.5 v 0.1 to 2.9 0.1 to 2.9 v input bias current ?0.4 ?0.4 a input resistance 2 2 m response time 48 db gain change 0.2 0.2 s power supply supply voltage 4.5 5.0 5.5 4.5 5.0 5.5 v power dissipation 90 90 mw vref input resistance 10 10 k quiescent supply current vpos 18 23 18 23 ma power down vpos, vgn < 50 mv 1.9 3.0 1.9 3.0 ma power-up response time 48 db gain, v out = 2 v p-p 0.6 0.6 s power-down response time 0.4 0.4 s
ad605 rev. d | page 5 of 20 absolute maximum ratings table 2. parameter rating supply voltage +v s pin 12, pin 13 (with pin 4, pin 5 = 0 v) 6.5 v input voltage pin 1 to pin 3, pin 6 to pin 9, pin 16 vpos, 0 internal power dissipation 16-lead pdip 1.4 w 16-lead soic_n 1.2 w operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature, soldering 60 sec 300c thermal resistance ja 16-lead pdip 85c/w 16-lead soic_n 100c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad605 rev. d | page 6 of 20 pin configuration and fu nction descriptions 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad605 vgn1 vpos fbk1 out1 vref ?in1 +in1 gnd1 out2 fbk2 vpos gnd2 +in2 ?in2 vgn2 vocm 00541-002 figure 2. pin configuration table 3. pin function descriptions pin o. neonic description 1 vgn1 ch1 gain-control input and power-down pin. if grounded , device is off; otherwise, positive voltage increases gain. 2 ?in1 ch1 negative input. 3 +in1 ch1 positive input. 4 gnd1 ground. 5 gnd2 ground. 6 +in2 ch2 positive input. 7 ?in2 ch2 negative input. 8 vgn2 ch2 gain-control input and power-down pin. if ground ed, device is off; otherwise, positive voltage increases gain. 9 vocm input to this pin defines common-mode voltage for out1 and out2. 10 out2 ch2 output. 11 fbk2 feedback pin that selects gain range of ch2. 12 vpos positive supply. 13 vpos positive supply. 14 fbk1 feedback pin that selects gain range of ch1. 15 out1 ch1 output. 16 vref input to this pin sets gain scaling for both channels: 2.5 v = 20 db/v, and 1.67 v = 30 db/v.
ad605 rev. d | page 7 of 20 typical performance characteristics (per channel) v ref = 2.5 v (20 db/v scaling), f = 1 mhz, r l = 500 , c l = 5 pf, t a = 25c, v ss = 5 v. 40 ?20 30 20 10 0 ?10 00541-003 vgn (v) gain (db) 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 ?40c, +25c, +85c figure 3. gain vs. vgn vgn (v) gain (db) 50 ?20 40 20 10 0 ?10 30 fbk (open) fbk (short) 00541-004 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 figure 4. gain vs. vgn fo r different gain ranges 30db/v (v ref = 1.67v) 20db/v (v ref = 2.50v) actual actual 40 ?20 30 20 10 0 ?10 00541-005 vgn (v) gain (db) 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 figure 5. gain vs. vgn for different gain scalings gain scaling (dbv) 40.0 37.5 20.0 30.0 27.5 25.0 22.5 35.0 32.5 theoretical actual v ref (v) 1.25 1.50 1.75 2.00 2.25 2.50 00541-006 figure 6. gain scaling vs. v ref gain error (db) 3.0 2.5 ?3.0 0.20.71.21.72.22 .7 ?1.0 ?1.5 ?2.0 ?2.5 2.0 1.0 1.5 ?0.5 0.5 0 vgn (v) +25c +85c ?40c 00541-007 figure 7. gain error vs. vgn at three temperatures vgn (v) gain error (db) 2.0 1.5 ?2.0 0.2 0.7 1.2 1.7 2.2 2.7 0 ?0.5 ?1.0 ?1.5 1.0 0.5 f = 5mhz f = 10mhz 00541-008 f = 1mhz figure 8. gain error vs. vgn at three frequencies
ad605 rev. d | page 8 of 20 vgn (v) gain error 2.0 1.0 1.5 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0.2 0.7 1.7 1.2 2.2 2.7 00541-009 20db/v v ref = 2.50v 30db/v v ref = 1.67v figure 9. gain error vs. vgn for two gain scale values delta gain (db) percentage 20 6 0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 18 8 4 2 16 12 14 10 ? g(db) = g(ch1) ? g(ch2) n = 50 00541-010 figure 10. gain match, vgn1 = vgn2 = 1.0 v 00541-011 delta gain (db) percentage 20 6 0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 18 8 4 2 16 12 14 10 ? g(db) = g(ch1) ? g(ch2) n = 50 figure 11. gain match, vgn1 = vgn2 = 2.50 v frequency (hz) gain (db) 60 40 ?60 0 ?20 ?40 20 vgn = 2.9v (fbk = open) vgn = 2.9v (fbk = short) vgn = 1.5v (fbk = open) vgn = 1.5v (fbk = short) vgn = 0.1v (fbk = open) vgn = 0.1v (fbk = short) vgn = 0.0v 00541-013 100k 1m 10m 100m figure 12. ac response for three values of vgn vgn (v) v os (v) 2.525 2.475 0 2.520 2.495 2.490 2.485 2.480 2.515 2.510 2.500 2.505 v ocm = 2.50v ?40c +25c +85c 00541-014 0.5 1.0 1.5 2.0 2.5 3.0 figure 13. output offset vs . vgn at three temperatures 00541-015 vgn (v) 130 90 125 110 105 100 95 120 115 0 0.5 1.0 1.5 2.0 2.5 3.0 +85c +25c noise (nv/ hz) ?40c figure 14. output referred noise vs. vgn at three temperatures
ad605 rev. d | page 9 of 20 vgn (v) 1000 100 1 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 10 noise (nv/ hz) 00541-016 figure 15. input referred noise vs. vgn temperature (c) 2.00 1.75 1.60 1.95 1.80 1.70 1.65 1.90 1.85 vgn = 2.9v noise (nv/ hz) 00541-017 ?40 ?20?30 ?10 0 20 10 40 60 50 30 8070 90 figure 16. input referred noise vs. temperature frequency (hz) 1.90 1.85 1.60 1.80 1.75 1.70 1.65 vgn = 2.9v noise (nv/ hz) 00541-018 100k 1m 10m figure 17. input referred noise vs. frequency r source ( ? ) 1k 10 11 0 0 vgn = 2.9v r source alone noise (nv/ hz) 00541-019 100 10 1.0 0.1 figure 18. input referred noise vs. r source noise figure (db) 30 25 5 1k 1 100 10 15 10 20 vgn = 2.9v 00541-020 r source ( ? ) figure 19. noise figure vs. r source vgn (v) noise figure (db) 60 50 40 30 20 10 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 00541-021 r s = 50 ? figure 20. noise figure vs. vgn
ad605 rev. d | page 10 of 20 frequency (hz) harmonic distortion (dbc) ? 30 ?35 ?70 ?50 ?55 ?65 ?60 ?40 ?45 hd2 hd3 100k 1m 10m 100m 00541-022 v out = 1v p-p vgn = 1.0v figure 21. harmonic distortion vs. frequency vgn (v) harmonic distortion (dbc) ? 35 ?75 ?55 ?60 ?65 ?70 ?40 ?50 ?45 hd3 (10mhz) hd2 (10mhz) hd2 (1mhz) hd3 (1mhz) 00541-023 0.5 1.1 1.4 0.8 1.7 2.0 2.3 2.6 2.9 figure 22. harmonic distortion vs. vgn at 1 mhz and 10 mhz frequency (mhz) p out (dbm) ? 20 ?90 ?120 ?30 ?80 ?100 ?110 ?60 ?70 ?40 ?50 00541-024 9.92 9.96 10.00 10.02 10.04 f = 10mhz v out = 1v p-p vgn = 1.0v figure 23. intermodulation distortion 15 ?20 10 0 ?5 ?10 ?15 5 freq = 10mhz freq = 1mhz input generator limit = 21dbm 00541-025 vgn (v) p in (dbm) 0.1 2.9 2.5 2.1 1.7 1.3 0.9 0.5 figure 24. 1 db compression vs. vgn 35 ?5 30 15 10 5 0 25 20 v out = 1v p-p f = 1mhz f = 10mhz 00541-026 vgn (v) intercept (dbm) 0.6 1.0 1.4 1.8 2.2 2.6 3.0 figure 25. third-order intercep t vs. vgn at 1 mhz and 10 mhz 100ns/div ?400mv/di v v out = 2v p-p vgn = 1.5v 2 v 2v 253ns 1.253s trig'd 00541-027 figure 26. large signal pulse response
ad605 rev. d | page 11 of 20 100ns/div 40mv (div) v out = 200mv p-p vgn = 1.5v 200 ?200 253ns 1.253s trig'd 00541-028 figure 27. small signal pulse response vgn (v) 2.9v 0.0v 10 0% 100 90 500mv 200ns 500mv 00541-029 figure 28. power-up/power-down response vgn (v) 2.9v 0.1v 10 0% 100 90 500mv 100ns 500mv 0 0541-030 figure 29. gain response frequency (hz) crosstalk (db) vgn1 = 1v v out1 = 1v p-p v in2 = gnd vgn2 = 2.9v vgn2 = 2.5v vgn2 = 2.0v vgn2 = 0.1v 00541-031 ? 30 ?40 ?60 ?50 ?70 ?80 ?90 100k 1m 10m 100m figure 30. crosstalk (ch1 to ch2) vs. frequency for four values of vgn2 0 ?10 ?60 ?20 ?30 ?50 ?40 cmrr (db) v in = 0dbm vgn = 2.9v vgn = 2.5v vgn = 2.0v vgn = 0.1v 00541-032 frequency (hz) 100k 1m 10m 100m figure 31. common-mode rejection ratio (cmrr) vs. frequency for four values of vgn frequency (hz) input impedance ( ? ) 180 175 140 160 155 145 150 170 165 vgn = 2.9v 00541-033 100k 1m 10m 100m figure 32. input impedance vs. frequency
ad605 rev. d | page 12 of 20 temperature (c) supply current (ma) 00541-034 25 15 20 10 50 0 ?40 ?20 0 20 10 ?10 ?30 40 60 8070 50 30 90 +i s (ad605) +i s (vgn = 0) frequency (hz) group delay (ns) vgn = 0.1v vgn = 2.9v 00541-035 16 12 14 10 6 8 4 100k 1m 10m 100m figure 34. group delay vs. frequency figure 33. supply current (one channel) vs. temperature
ad605 rev. d | page 13 of 20 theory of operation the ad605 is a dual channel, low noise variable gain amplifier. figure 35 shows the simplified block diagram of one channel. each channel consists of a single-supply x-amp? (hereafter called dsx, differential single-supply x-amp) comprised of: ? precision passive attenuator (differential ladder) ? gain control block ? vocm buffer with supply splitting resistors r3 and r4 ? active feedback amplifier 1 (afa) with gain setting resistors r1 and r2 the linear-in-db gain response of the ad605 can generally be described by equation 1. g (db) = ( gain scaling (db/v)) ( gain control (v)) ? (19 db ? (14 db) ( fb )) (1) where: fb = 0, if fbk-to-out are shorted. fb = 1, if fbk-to-out is open. each channel provides between ?14 db to +34.4 db through 0 db to +48.4 db of gain depending on the value of the resistance connected between pin fbk and pin out. the center 40 db of gain is exactly linear-in-db while the gain error increases at the top and bottom of the range. the gain is set by the gain control voltage (vgn). the vref input establishes the gain scaling. the useful gain scaling range is between 20 db/v and 40 db/v for a vref voltage of 2.5 v and 1.25 v, respectively. for example, if fbk to out were shorted and vref were set to 2.50 v (to establish a gain scaling of 20 db/v), the gain equation would simplify to g (db) = (20 (db/v)) ( vgn (v)) C 19 db (2) the desired gain can then be achieved by setting the unipolar gain control (vgn) to a voltage within its nominal operating range of 0.25 v to 2.65 v (for 20 db/v gain scaling). the gain is monotonic for a complete gain control range of 0.1 v to 2.9 v. maximum gain can be achieved at a vgn of 2.9 v. because the two channels are identical, only channel 1 is used to describe their operation. vref and vocm are the only inputs that are shared by the two channels, and because they are normally ac grounds, crosstalk between the two channels is minimized. for highest gain scaling accuracy, vref should have an external low impedance voltage source. for low accuracy 20 db/v applications, the vref input can be decoupled with a capacitor to ground. in this mode, the gain scaling is determined by the midpoint between +vcc and gnd; therefore, care should be taken to control the supply voltage to 5 v. the input resistance looking into the vref pin is 10 k 20%. the ad605 is a single-supply circuit and the vocm pin is used to establish the dc level of the midpoint of this portion of the circuit. vocm needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 v, gnd). however, if the dc level of the output is important to the user (see the applications section of the ad9050 data sheet for an example), then vocm can be specifically set. the input resistance looking into the vocm pin is 45 k 20%. 1 to understand the ac tive-feedback am plifier topology, refer to the ad830 data sheet. the ad830 is a practica l implementation of the idea. r1 820? vref vgn vpos v ocm r3 200k ? c3 out distributed g m 175 ? 175 ? g1 gain control ao g2 r2 20? r4 200k ? ext +in ?in fbk 3.36k ? differential attenuator ext c2 c1 00541-036 + + + + figure 35. simplified block diagram of a single channel of the ad605
ad605 rev. d | page 14 of 20 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r 1.5r r rrrrr r r r r r r r r ? 6.908db ? 13.82db ? 20.72db ? 27.63db ? 34.54db ? 41.45db ? 48.36db +in mid ?in note: r = 96 ? 1.5r = 144 ? 175 ? 175 ? 00541-037 figure 36. r-1.5r dual ladder network differential ladder (attenuator) the attenuator before the fixed gain amplifier is realized by a differential 7-stage r-1.5r resistive ladder network with an untrimmed input resistance of 175 single-ended or 350 differentially. the signal applied at the input of the ladder network is attenuated by 6.908 db per tap; thus, the attenuation at the first tap is 6.908 db, at the second, 13.816 db, and so on all the way to the last tap where the attenuation is 48.356 db (see figure 36 ). a unique circuit technique is used to interpolate continuously between the tap points, thereby providing continuous attenuation from 0 db to ?48.36 db. one can think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer. since the dsx is a single-supply circuit, some means of biasing its inputs must be provided. node mid together with the vocm buffer performs this function. without internal biasing, external biasing is required. if not done carefully, the biasing network can introduce additional noise and offsets. by providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the dsx. it should be made clear again that the input to the dsx is still fully differential if driven differentially, that is, pin +in and pin ?in see the same signal but with opposite polarity. what changes is the load as seen by the driver; it is 175 when each input is driven single-ended, but 350 when driven differentially. this can be easily explained when thinking of the ladder network as two 175 resistors connected back-to-back with the middle node, mid, being biased by the vocm buffer. a differential signal applied between nodes +in and ?in results in zero current into node mid, but a single-ended signal applied to either input +in or ?in, while the other input is ac grounded, causes the current delivered by the source to flow into the vocm buffer via node mid. a feature of the x-amp architecture is that the output-referred noise is constant vs. gain over most of the gain range. referring to figure 36 , the tap resistance is approximately equal for all taps within the ladder, excluding the end sections. the resistance seen looking into each tap is 54.4 , which makes 0.95 nv/hz of johnson noise spectral density. because there are two attenuators, the overall noise contribution of the ladder network is 2 times 0.95 nv/hz or 1.34 nv/hz, a large fraction of the total dsx noise. the rest of the dsx circuit components contribute another 1.20 nv/hz, which together with the attenuator produces 1.8 nv/hz of total dsx input, referred noise. ac coupling the dsx is a single-supply circuit; therefore, its inputs need to be ac-coupled to accommodate ground-based signals. external capacitor c1 and capacitor c2 in figure 35 level shift the input signal from ground to the dc value established by vocm (nominal 2.5 v). c1 and c2, together with the 175 looking into each of dsx inputs (+in and ?in), act as high-pass filters with corner frequencies depending on the values chosen for c1 and c2. for example, if c1 and c2 are 0.1 f, then together with the 175 input resistance of each side of the differential ladder of the dsx, a ?3 db high-pass corner at 9.1 khz is formed. if the dsx output needs to be ground referenced, then another ac coupling capacitor is required for level shifting. this capacitor also eliminates any dc offsets contributed by the dsx. with a nominal load of 500 and a 0.1 f coupling capacitor, this adds a high-pass filter with ?3 db corner frequency at about 3.2 khz. the choice for all three of these coupling capacitors depends on the application. they should allow the signals of interest to pass unattenuated, while at the same time, they can be used to limit the low frequency noise in the system. gain control interface the gain control interface provides an input resistance of approximately 2 m at pin vgn1 and gain scaling factors from 20 db/v to 40 db/v for vref input voltages of 2.5 v to 1.25 v, respectively. the gain varies linearly in db for the center 40 db of gain range, that is, for vgn equal to 0.4 v to 2.4 v for the 20 db/v scale, and 0.25 v to 1.25 v for the 40 db/v scale. figure 37 shows the ideal gain curves when the fbk-to-out connection is shorted as described by the following equations: g (20 db/v) = 20 vgn ? 19, v ref = 2.500 v (3) g (30 db/v) = 30 vgn ? 19, v ref = 1.6666 v (4) g (40 db/v) = 40 vgn ? 19, v ref = 1.250 v (5) from the equations one can see that all gain curves intercept at the same ?19 db point; this intercept is 14 db higher (?5 db) if the fbk-to-out connection is left open. outside of the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 db of range. for a given gain scaling, one can calculate v ref as scalegain v ref db/v20v2.500 u (6)
ad605 rev. d | page 15 of 20 35 30 25 20 15 10 5 0 ?5 ?10 ?15 ?20 gain (db) 40db/v 30db/v 20db/v linear-in-db range of ad605 1.0 0.5 1.5 2.0 2.5 3.0 gain control voltage 0 0541-038 figure 37. ideal gain curves vs. v ref usable gain control voltage ranges are 0.1 v to 2.9 v for the 20 db/v scale and 0.1 v to 1.45 v for the 40 db/v scale. vgn voltages of less than 0.1 v are not used for gain control because below 50 mv the channel is powered down. this can be used to conserve power and at the same time gate-off the signal. the supply current for a powered-down channel is 1.9 ma, and the response time to power the device on or off is less than 1 s. active feedback amplifier (fixed gain amp) to achieve single-supply operation and a fully differential input to the dsx, an active feedback amplifier (afa) was used. the afa is an op amp with two g m stages; one of the active stages is used in the feedback path (therefore the name), while the other is used as a differential input. note that the differential input is an open-loop g m stage that requires that it be highly linear over the expected input signal range. in this design, the g m stage that senses the voltages on the attenuator is a distributed one; for example, there are as many g m stages as there are taps on the ladder network. only a few of them are on at any one time, depending on the gain control voltage. the afa makes a differential input structure possible since one of its inputs (g1) is fully differential; this input is made up of a distributed g m stage. the second input (g2) is used for feedback. the output of g1 is some function of the voltages sensed on the attenuator taps that is applied to a high-gain amplifier (a0). because of negative feedback, the differential input to the high gain amplifier is zero; this in turn implies that the differential input voltage to g2 times g m2 (the transconductance of g2) is equal to the differential input voltage to g1 times g m1 (the transconductance of g1). therefore the overall gain function of the afa is 2 21 2 1 r rr gm gm v v atten out = (7) where: v out is the output voltage. v at ten is the effective voltage sensed on the attenuator. ( r1 + r2 )/ r2 = 42. g m1 / g m2 = 1.25; the overall gain is therefore 52.5 (34.4 db). the afa has additional features: inverting the output signal by switching the positive and negative input to the ladder network; the possibility of using the ?in input as a second signal input; and independent control of the dsx common-mode voltage. under normal operating conditions, it is best to connect a decoupling capacitor to pin vocm, in which case, the common- mode voltage of the dsx is half of the supply voltage; this allows for maximum signal swing. nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to vocm. it can also be used as another signal input, the only limitation being the rather low slew rate of the vocm buffer. if the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the dsx; again, this is done for level shifting and to eliminate any dc offsets contributed by the dsx (see the ac coupling section). the gain range of the dsx is programmable by a resistor connected between pin fbk and pin out. the possible ranges are ?14 db to +34.4 db when the pins are shorted together, or 0 db to +48.4 db when fbk is left open. note that for the higher gain range, the bandwidth of the amplifier is reduced by a factor of five to about 8 mhz because the gain increased by 14 db. this is the case for any constant gain bandwidth product amplifier that includes the active feedback amplifier.
ad605 rev. d | page 16 of 20 applications the basic circuit in figure 38 shows the connections for one channel of the ad605 with a gain range of ?14 db to +34.4 db. the signal is applied at pin 3. the ac coupling capacitors before pin ?in1 and pin +in1 should be selected according to the required lower cutoff frequency. in this example, the 0.1 f capacitors, together with the 175 of each of the dsx input pins, provide a ?3 db high pass corner of about 9.1 khz. the upper cutoff frequency is determined by the amplifier and is 40 mhz. 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 vref gnd1 +in1 ?in1 vgn1 out1 fbk1 vpos ?in2 +in2 gnd2 vpos fbk2 out2 vocm vgn2 ad605 vgn v in 0.1f 0.1f 0.1f 5v 0.1f out 2.500v 0 0541-039 figure 38. basic connections for a single channel as shown in figure 38 , the output is ac-coupled for optimum performance. in the case of connecting to the 10-bit, 40 msps adc, ad9050 , ac coupling can be eliminated as long as pin vocm is biased by the same 3.3 v common-mode voltage as the ad9050 . pin vref requires a voltage of 1.25 v to 2.5 v, with gain scaling between 40 db/v and 20 db/v, respectively. voltage vgn controls the gain; its nominal operating range is from 0.25 v to 2.65 v for 20 db/v gain scaling, and 0.125 v to 1.325 v for 40 db/v scaling. when this pin is taken to ground, the channel powers down and disables its output. connecting two amplifiers to double the gain range figure 39 shows the two channels of the ad605 connected in series to provide a total gain range of 96.8 db. when r1 and r2 are shorts, the gain range is from ?28 db to +68.8 db with a slightly reduced bandwidth of about 30 mhz. the reduction in bandwidth is due to two identical low-pass circuits being connected in series; in the case of two identical single-pole low- pass filters, the bandwidth would be reduced by exactly 2. if r1 and r2 are replaced by open circuits, that is, pin fbk1 and pin fbk2 are left unconnected, then the gain range shifts up by 28 db to 0 db to 96.8 db. as previously noted, the bandwidth of each individual channel is reduced by a factor of 5 to about 8 mhz because the gain increased by 14 db. in addition, there is still the 2 reduction because of the series connection of the two channels that results in a final bandwidth of the higher gain version of about 6 mhz. 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 vref gnd1 +in1 ?in1 vgn1 out1 fbk1 vpos ?in2 +in2 gnd2 vpos fbk2 out2 vocm vgn2 ad605 c2 0.1f vgn v in r1 5v out 2.500v c1 0.1f c3 0.1f c4 0.1f c6 0.1f r2 c5 0.1f 00541-040 figure 39. doubling the gain range with two amplifiers two other easy combinations are possible to provide a gain range of ?14 db to +82.8 db: make r1 a short and r2 an open, or make r1 an open and r2 a short. the bandwidth for both of these cases is dominated by the channel that is set to the higher gain and is about 8 mhz. from a noise standpoint, the second choice is the best because by increasing the gain of the first amplifier, the second amplifiers noise has less of an impact on the total output noise. one further observation regarding noise is that by increasing the gain, the output noise increases proportionally; therefore, there is no increase in signal-to-noise ratio. it actually stays fixed. it should be noted that by selecting the appropriate values of r1 and r2, any gain range between ?28 db to +68.8 db and 0 db to +96.8 db can be achieved with the circuit in figure 39 . when using any value other than shorts and opens for r1 and r2, the final value of the gain range depends on the external resistors matching the on-chip resistors. since the internal resistors can vary by as much as 20%, the actual values for a particular gain have to be determined empirically. note that the two channels within one part match quite well; therefore, r1 tracks r2 in figure 39 . c3 is not required because the common-mode voltage at pin out1 should be identical to the one at pin +in2 and pin ?in2. however, since only 1 mv of offset at the output of the first dsx introduces an offset of 53 mv when the second dsx is set to the maximum gain of the lowest gain range (34.4 db), and 263 mv when set to the maximum gain of the highest gain range (48.4 db), it is important to include ac coupling to get the maximum dynamic range at the output of the cascaded amplifiers. c5 is necessary if the output signal needs to be referenced to any common-mode level other than half of the supply as is provided by pin out2.
ad605 rev. d | page 17 of 20 figure 40 shows the gain vs. vgn for the circuit in figure 39 at 1 mhz and the lowest gain range (?14 db to +34.4 db). note that the gain scaling is 40 db/v, double the 20 db/v of an individual dsx; this is the result of the parallel connection of the gain control inputs, vgn1 and vgn2. one could of course also sequentially increase the gain by first increasing the gain of channel 1 and then channel 2. in this case, vgn1 and vgn2 are driven from separate voltage sources, for instance two separate dacs. figure 41 shows the gain error of figure 39 . 80 ?40 f = 1mhz actual 0 70 20 ?10 ?20 ?30 50 30 60 40 10 00541-041 vgn (v) gain (db) theoretical 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 figure 40. gain vs. vgn for the circuit in figure 39 vgn (v) gain error (db) 4 3 ?4 0 ?1 ?2 ?3 2 1 f = 1mhz 00541-042 0.2 0.7 1.2 1.7 2.2 2.7 figure 41. gain error vs. vgn for the circuit in figure 39
ad605 rev. d | page 18 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ab 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) pin 1 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 42. 16-lead plastic dual in-line package [pdip] (n-16) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 16 9 8 1 4.00 (0.1575) 3.80 (0.1496) 10.00 (0.3937) 9.80 (0.3858) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2283) seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 8 0 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 45 figure 43. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches)
ad605 rev. d | page 19 of 20 ordering guide model temperature range package description package option ad605an ?40c to +85c 16-lead pdip n-16 AD605ANZ 1 ?40c to +85c 16-lead pdip n-16 ad605ar ?40c to +85c 16-lead soic_n r-16 ad605ar-reel ?40c to +85c 16-lead soic_n, 13" reel r-16 ad605ar-reel7 ?40c to +85c 16-lead soic_n, 7" reel r-16 ad605arz 1 ?40c to +85c 16-lead soic_n r-16 ad605arz-rl 1 ?40c to +85c 16-lead soic_n, 13" reel r-16 ad605arz-rl7 1 ?40c to +85c 16-lead soic_n, 7" reel r-16 ad605bn ?40c to +85c 16-lead pdip n-16 ad605br ?40c to +85c 16-lead soic_n r-16 ad605br-reel ?40c to +85c 16-lead soic_n, 13" reel r-16 ad605br-reel7 ?40c to +85c 16-lead soic_n, 7" reel r-16 ad605brz 1 ?40c to +85c 16-lead soic_n r-16 ad605brz-rl 1 ?40c to +85c 16-lead soic_n, 13" reel r-16 ad605brz-rl7 1 ?40c to +85c 16-lead soic_n, 7" reel r-16 ad605-eb evaluation board ad605achips die 1 z = pb-free part.
ad605 rev. d | page 20 of 20 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c00541-0-1/06(d)

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